“Today, most conducted EMI problems are caused by common-mode noise. Also, most common-mode noise problems are caused by parasitic capacitance in the power supply. The following discussion will focus on what happens when parasitic capacitance couples directly to the power input wires.
Today, most conducted EMI problems are caused by common-mode noise. Also, most common-mode noise problems are caused by parasitic capacitance in the power supply. The following discussion will focus on what happens when parasitic capacitance couples directly to the power input wires.
1. Only a few fF of stray capacitance can cause EMI scan failure. Essentially, switching power supplies have nodes that provide high dV/dt. The combination of parasitic capacitance and high dV/dt creates EMI problems. When the other end of the parasitic capacitance is connected to the power input, a small amount of current is pumped directly to the power line.
2. Check for parasitic capacitance in the power supply. We all remember from physics class that the capacitance between two conductors is proportional to the surface area of the conductors and inversely proportional to the distance between them. Look at every node in the circuit and pay particular attention to nodes with high dV/dt. Think about the surface area of that node in the circuit layout, and how far the node is from the board’s input lines. The drain and snubber circuits of switching MOSFETs are common culprits.
3. There are tricks to reducing the surface area. Try to use surface mount packages whenever possible. A FET in a vertical TO-220 package has a very large drain tab surface area, which unfortunately usually happens to be the node with the highest dV/dt. Try using surface mount DPAK or D2PAK FETs instead. Placing a primary ground plane on the low-level PCB below the DPAK tab provides good shielding of the bottom of the FET, which can significantly reduce parasitic capacitance.
Sometimes surface area is needed for heat dissipation. If you must use a TO-220 class FET with a heat sink, try connecting the heat sink to primary ground (not earth ground). Not only does this help shield the FETs, but it also helps reduce stray capacitance.
4. Keep the switch node away from the input connection. See the design example in Figure 1, where I ignore this simple principle.
Figure 1: Putting input routing too close to nodes with high dV/dt increases conducted EMI.
I reduced the noise by about 6dB by simply tweaking the board (no circuit changes). See Figures 2 and 3 for the measurement results. In some cases, routing the input lines close to high dV/dt can even damage the Common Mode Coil (CMC).
Figure 2: EMI scanning from a board layout where the AC input is close to the switching circuit How to solve EMI problems caused by common mode noise on the board
Figure 3: EMI scan from board layout with large distance between AC input and switching circuit Have you ever experienced little to no improvement in EMI after significantly tightening the input filter? This is most likely due to some stray capacitance from some high dV/dt node coupling directly into the input line, effectively bypassing your CMC. To detect this condition, temporarily short the windings of the CMC on the PCB and place a secondary CMC in series with the board’s input wires. If there is a noticeable improvement, you will need to re-layout the board and pay extra attention to the placement and routing of the input connections.